74HC195
Layout symbol
4-bit parallel-access shift register: With PE high, each rising edge of CP shifts the data along Q0–Q3, with the J and K̅ inputs setting the first stage (tie them together for a simple data input). With PE low, the clock loads D0–D3 instead. MR low clears the register. Same pinout as the 74LS195.
integrated circuit
IC
chip
7400 series
logic
shift register
74HCT195
74LS195
74195
Details
- Reference Character
- U
- Default Value
- 74HC195
- Author
- Circuit Canvas
- License
- Circuit Canvas Parts License
- Library
- Circuit Canvas Library
