74LS155
Schematic symbol
Dual 2-to-4 line decoder/demultiplexer: Both halves share the address inputs A and B, which pick one of four active-low outputs in each half. Half 1 is enabled by 1G low and 1C high, half 2 by 2G and 2C both low. Tie 1C to 2C and 1G to 2G to make a 3-to-8 decoder, with C as the third address bit.
integrated circuit
IC
chip
7400 series
logic
decoder
demultiplexer
TTL
74155
74HC155
Details
- Reference Character
- U
- Default Value
- 74LS155
- Author
- Circuit Canvas
- License
- Circuit Canvas Parts License
- Library
- Circuit Canvas Library
